Package Declaration and Package Body in VHDL

Objective: Declaring a package in VHDL which consist of full adder function or procedure and using the same package design 4 bit Ripple Carry Adder(RCA)
---Full Adder function is declared in package  to design 4 bit RCA


library IEEE;
use IEEE.STD_LOGIC_1164.all;
--------Package Declaration--------
package fapkgfn is
subtype bit4 is std_logic_vector(3 downto 0);
subtype bit2 is std_logic_vector(1 downto 0);
subtype bit1 is std_logic;
function fa(a,b,c:std_logic) return bit2;

end fapkgfn;


-------Package Body ------
package body fapkgfn is
function fa(a,b,c:std_logic) return bit2 is

variable s,c1:std_logic;

begin
s:= a xor b xor c;
c1:=(a and b) or (b and c)or (c and a);
return s&c1;
end fa;
end fapkgfn;

--------Using Package, design 4 bit RCA----

library WORK;
use work.fapkgfn.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.all;---needed when we use & (concatenate) opearation

ntity rcapackage is
    Port ( a,b : in bit4; --STD_LOGIC;
           s : out  bit4;--STD_LOGIC;
           cin : in  bit1;--STD_LOGIC;
           cout : out  bit1);
end rcapackage;

architecture Behavioral of rcapackage is
signal c1,c2,c3,c4:bit2;

begin
c1<= fa(a(0),b(0),cin);
c2<=fa(a(1),b(1),c1(0));
c3<=fa(a(2),b(2),c2(0));
c4<=fa(a(3),b(3),c3(0));
s<=c4(1)& c3(1) & c2(1) & C1(1);
cout<=c4(0);

end Behavioral;

---Full Adder procedure  is declared in package  to design 4 bit RCA

library IEEE;
use IEEE.STD_LOGIC_1164.all;
--------Package Declaration--------
package fa_proc is
procedure fa (a,b,c:in std_logic; signal sum,cout:out std_logic);
end fa_proc;
------Package Body ------
package body fa_proc is
procedure fa (a,b,c: in std_logic;signal sum,cout:out std_logic) is
 begin
 sum<= a xor b xor c;
 cout<=(a and b) or (b and c) or (c and a);
 end fa;
end fa_proc;

-------Using Package, design 4 bit RCA----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.fa_proc.all;

entity rca is
    Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
           sum : out  STD_LOGIC_VECTOR (3 downto 0);
           cin : in  STD_LOGIC;
           carry : out  STD_LOGIC);
end rca;

architecture Behavioral of rca is
signal c1,c2,c3:std_logic;
begin
fa(a(0),b(0),cin,sum(0),c1);
fa(a(1),b(1),c1,sum(1),c2);
fa(a(2),b(2),c2,sum(2),c3);
fa(a(3),b(3),c3,sum(3),carry);

end Behavioral;