Sequence -1011
--Behavioral code of Mealy FSM for 1011 sequence detector
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sd1011 is
Port ( x,clk : in std_logic;
z : out std_logic);
end sd1011;
architecture Behavioral of sd1011 is
signal state,nextstate:integer range 0 to 3;
begin
process(state,x)
begin
case state is
when 0 => if x='0' then nextstate<=0;z<='0';
else nextstate<=1;z<='0'; end if;
when 1 => if x='0' then nextstate<=2;z<='0';
else nextstate<=1;z<='0';end if;
when 2 => if x='0' then nextstate<=0;z<='0';
else nextstate<=3;z<='0';end if;
when 3 => if x='0' then nextstate<=2;z<='0';
else nextstate<=1;z<='1';end if;
when others=> null;
end case; end process;
process(clk)
begin
if (rising_edge(clk)) then
state<=nextstate;
end if;
end process;
end Behavioral;
---- Second way to write same Mealy FSM behavioral model
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sdz1011 is
Port ( x,clk : in std_logic;
z : out std_logic);
end sdz1011;
architecture Behavioral of sdz1011 is
signal state:integer range 0 to 3;
begin
process(clk)
begin
if (rising_edge(clk)) then
case state is
when 0 => if x='0' then state<=0;else state<=1; end if;
when 1 => if x='0' then state<=2;else state<=1; end if;
when 2 => if x='0' then state<=0;else state<=3; end if;
when 3 => if x='0' then state<=2;else state<=1; end if;
when others=> null;
end case;
if (state=3 and x='1') then z<='1'; else z<='0'; end if;
end if;
end process;
end Behavioral;
VHDL code for Sequence/Pattern Detector (0110)
---Dataflow model for the sequence 0110
---equations are from Mealy FSM + guidelines to reduce amount of logic(refer roth book)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sdd0110 is
Port ( x,clk : in std_logic;
z : out std_logic);
end sdd0110;
architecture Behavioral of sdd0110 is
signal a,b:std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
a<= x and not b;
b<= x and ( a or b);
end if;
end process;
z<= not x and a and b;
end Behavioral;
--Behavioral code of Mealy FSM for 1011 sequence detector
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sd1011 is
Port ( x,clk : in std_logic;
z : out std_logic);
end sd1011;
architecture Behavioral of sd1011 is
signal state,nextstate:integer range 0 to 3;
begin
process(state,x)
begin
case state is
when 0 => if x='0' then nextstate<=0;z<='0';
else nextstate<=1;z<='0'; end if;
when 1 => if x='0' then nextstate<=2;z<='0';
else nextstate<=1;z<='0';end if;
when 2 => if x='0' then nextstate<=0;z<='0';
else nextstate<=3;z<='0';end if;
when 3 => if x='0' then nextstate<=2;z<='0';
else nextstate<=1;z<='1';end if;
when others=> null;
end case; end process;
process(clk)
begin
if (rising_edge(clk)) then
state<=nextstate;
end if;
end process;
end Behavioral;
---- Second way to write same Mealy FSM behavioral model
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sdz1011 is
Port ( x,clk : in std_logic;
z : out std_logic);
end sdz1011;
architecture Behavioral of sdz1011 is
signal state:integer range 0 to 3;
begin
process(clk)
begin
if (rising_edge(clk)) then
case state is
when 0 => if x='0' then state<=0;else state<=1; end if;
when 1 => if x='0' then state<=2;else state<=1; end if;
when 2 => if x='0' then state<=0;else state<=3; end if;
when 3 => if x='0' then state<=2;else state<=1; end if;
when others=> null;
end case;
if (state=3 and x='1') then z<='1'; else z<='0'; end if;
end if;
end process;
end Behavioral;
VHDL code for Sequence/Pattern Detector (0110)
---Dataflow model for the sequence 0110
---equations are from Mealy FSM + guidelines to reduce amount of logic(refer roth book)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sdd0110 is
Port ( x,clk : in std_logic;
z : out std_logic);
end sdd0110;
architecture Behavioral of sdd0110 is
signal a,b:std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
a<= x and not b;
b<= x and ( a or b);
end if;
end process;
z<= not x and a and b;
end Behavioral;
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