Assignment 3

1. What is clock skew? Explain with neat diagram types of clock skew OR With suitable sketches and circuit diagrams briefly explain the concept of clock skew and clock jitter

2. Design a Mealy FSM to detect an overlapping sequence (i) “1011” (ii) 1101 and describe using VHDL.

3. Explain with neat diagram how asynchronous inputs are interfaced with synchronous digital circuits. (Hint: Synchronizer)

4. Write a VHDL code for up counter with synchronous and with asynchronous reset.

5. What is gating of clock? What are disadvantages of gating clock?

6.  Write a VHDL code  to  describe a 4 bit counter which  counts  only even numbers .0,2, 4,...,14,  0,2, ...

7. Implement using ‘generate’ statement a 4 bit shift register use D F-F as a component OR  Write a VHDL code using generate statement for 4-bit serial in serial out shift register using single D flip flop as a component.

8. Design a Moore FSM to design an overlapping sequence “1001” and describe using VHDL

9. Write a VHDL code for (i) Synchronous reset D flip flop (ii) JK flip-flop (iii) D flip-flop with asynchronous set and reset inputs. Draw entity diagram also.

10. Write a short note on Meta-stability. OR Explain the concept of meta-stability with suitable example. OR Explain the concept of meta-stability with suitable example. Which are the reasons because of which circuit enters into meta-stable state?  

11. Write a VHDL code for up down counter with control input up/down.

12. Describe the functioning of 'Process' statement with proper syntax. Write a VHDL code for positive edge triggered 'D' flip-flop with synchronous ‘Clear’ input.               

13. Convert following state table into its equivalent Moore model state diagram, and write a VHDL model for the same state diagram.

14. a) Write a VHDL model for single port RAM

       b) List and describe the i/o signals for dual port RAM and write a VHDL

15. Write VHDL code for 4 bit ripple counter using JK flip flop. Use structural modeling for writing the same.

16. Draw a state diagram for a sequence detector’1011’ which is realized as a Mealy machine.  Write a VHDL code for the above said Mealy machine.

17. Design and describe using VHDL a Data path to implement operations A=A+B, A=A-B, where A and B are 8 bit registers.

18. Explain the  working  of 4 input  bus  arbiter  having  fix  priority  with  the  help of state  diagram description  for  the  same.

19. Design  a two  input  'N  bit'  serial  adder  and  write  a VHDL  description  for  the same.(hint:  if  A and B are the  inputs  then  Sum=A+ B at every  clock  and cout  is  a carry  bit  which  is  stored for  further  additions  at  reset  the  stored  carry bit  is  cleared).