Generate Statement Example 2: Shift Register using D flip-flop as component

-----D flip-flop code-------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff is
    Port ( d,clk : in  STD_LOGIC;
           q : out  STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
process(clk)
begin
if rising_edge(clk) then
q<=d;
end if;
end process;

end Behavioral;


---------Main Program------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shiftreg is
    Port ( din,clk : in  STD_LOGIC;
           dout : out  STD_LOGIC);
end shiftreg;

architecture structural of shiftreg is

component dff 
port(d,clk:in std_logic;
q:out std_logic);
end component;

signal s : std_logic_vector(4 downto 0);

begin
s(0)<=din;
sr:for i in 0 to 3 generate
dff1: dff port map (s(i),clk,s(i+1)) ;
end generate;
dout<=s(4);
end structural;