Configuration Statement and Configuration Declaration in VHDL with example

Configuration statement
Objective: To design a full adder using two half adders which are written in different styles of modeling. For example one half adder using structural modeling and another using behavioral modeling.Half adders are given same architecture name.

--Half Adder behavioral 

entity ha is
    Port ( a,b : in  STD_LOGIC;
           s,c : out  STD_LOGIC);
end ha;

architecture Behavioral of ha is

begin
process(a,b) is
begin
if(a='0' and b='0') then s<='0'; c<='0';
elsif(a='0' and b='1') then s<='1'; c<='0';
elsif(a='1' and b='0') then s<='1'; c<='0';
else s<='0'; c<='1';
end if; end process;

end Behavioral;

---Half Adder using structural modelling
--note or gate declared but never used still binding is possible from the main program
entity xor_2 is
port (x,y:in std_logic;
z: out std_logic);
end xor_2;
architecture dataflow of xor_2 is
begin
z<= x xor y;
end dataflow;

-----or gate component----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_2 is
port (x,y:in std_logic;
z: out std_logic);
end or_2;
architecture dataflow of or_2 is
begin
z<= x or y;
end dataflow;

-----and gate component----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_2 is
port (x,y:in std_logic;
z: out std_logic);
end and_2;
architecture dataflow of and_2 is
begin
z<= x and y;
end dataflow;
--------main program-----------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ha is
    Port ( a,b : in  STD_LOGIC;
           s,c : out  STD_LOGIC);
end ha;

architecture structural of ha is

component xor_2 is
port (x,y:in std_logic;
z: out std_logic);
end component;
component and_2 is
port (x,y:in std_logic;
z: out std_logic);
end component;
begin
xor1: xor_2 port map (a,b,s);
and1: and_2 port map (a,b,c);

end structural;

---Full Adder structural program
entity fa is
    Port ( a,b,c : in  STD_LOGIC;
           sum,carry : out  STD_LOGIC);
end fa;

architecture fastructural of fa is
component ha is
port(a,b: in std_logic;
s,c:out std_logic);
end component;

component or_2 is
port(x,y:in std_logic;
z:out std_logic);
end component;
for ha1:ha use entity work.ha(Behavioral);--configuration statement binds instance ha1 with ha(behavioral)
for ha2:ha use entity work.ha(structural);--configuration statement binds instance ha2 with ha(structural)
signal s1,c1,c2: std_logic;
begin

ha1: ha port map(a,b,s1,c1);
ha2: ha port map(s1,c,sum,c2);
or1: or_2 port map(c1,c2,carry);


end fastructural;