Assignment -2

                                            Assignment 2                                  Class: T.E (A&B)

1.       Write behavioral VHDL code for tristate buffer.

2.       Write VHDL code to describe 4-bit Binary to Gray converter. OR Write a VHDL code to  describe  4 input  binary to  gray converter

3.       Describe using VHDL code for 8-bit comparator.  If A and B are 8-bit numbers.  comparator  has  three  output  A >B, A < B and  A= B. use  4-bit comparator  to  implement  8-bit comparator.

4.       Write a VHDL  code for  full  adder  using  three  styles of modeling

5.       Write a VHDL  code  for  even  parity generator  having 8 input  bits and  1 bit parity  output. OR Write VHDL code for even parity generator

6.       Write a syntax and explain with example generate statement OR Write syntax of For- Generate. Give suitable example

7.       Design and describe using VHDL, 4 bit one hot decoder with ENABLE input and VALID output.  If ENABLE=0 then  VALID= 1 otherwise  VALID=0 and  only  one  of the  16 output is  active.

8.       Write a VHDL code to  describe  a 5-bit  incrementer  which increments  the input  by  one at the  output  using this  full  adder.

9.       Write a VHDL code to describe a 4 input gray to binary converter

10.   Write behavioral VHDL code for 3:8 decoder

11.   Write VHDL code for 4:1 multiplexer using (i)case statement (ii)with-select

12.   Write a VHDL code for N-bit parity generator using “generic”.

13.   Write structural VHDL model for half adder

14.   Declare  Full Adder  component as a package, and  using  the  same  package write  a VHDL  code  for  4 bit  Ripple  Adder

15.   Describe 'lf-then-else' VHDL statement with proper syntax.  Write a VHDL code for 4: 1 multiplexer using 'lf-then-else’ statement.

16.   Explain the functioning of ‘Case’ statement used in VHDL programming. Write a VHDL code for 3:8 decoder using ‘case’ statement.

17.   Using two half adder circuits draw the circuit for full adder. Write a VHDL code for full adder using structural type of modeling.

18.   Write a VHDL model for 8 tri-state buffers using 'generic' statement.(Note: use common Enable for all tri-state buffers)

19.   Write a VHDL model for HEX to Common Anode type seven-segment decoder using 'with-select' statement.