Package Declaration and Package Body in VHDL

Objective: Declaring a package in VHDL which consist of full adder function or procedure and using the same package design 4 bit Ripple Carry Adder(RCA)
---Full Adder function is declared in package  to design 4 bit RCA


library IEEE;
use IEEE.STD_LOGIC_1164.all;
--------Package Declaration--------
package fapkgfn is
subtype bit4 is std_logic_vector(3 downto 0);
subtype bit2 is std_logic_vector(1 downto 0);
subtype bit1 is std_logic;
function fa(a,b,c:std_logic) return bit2;

end fapkgfn;


-------Package Body ------
package body fapkgfn is
function fa(a,b,c:std_logic) return bit2 is

variable s,c1:std_logic;

begin
s:= a xor b xor c;
c1:=(a and b) or (b and c)or (c and a);
return s&c1;
end fa;
end fapkgfn;

--------Using Package, design 4 bit RCA----

library WORK;
use work.fapkgfn.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.all;---needed when we use & (concatenate) opearation

ntity rcapackage is
    Port ( a,b : in bit4; --STD_LOGIC;
           s : out  bit4;--STD_LOGIC;
           cin : in  bit1;--STD_LOGIC;
           cout : out  bit1);
end rcapackage;

architecture Behavioral of rcapackage is
signal c1,c2,c3,c4:bit2;

begin
c1<= fa(a(0),b(0),cin);
c2<=fa(a(1),b(1),c1(0));
c3<=fa(a(2),b(2),c2(0));
c4<=fa(a(3),b(3),c3(0));
s<=c4(1)& c3(1) & c2(1) & C1(1);
cout<=c4(0);

end Behavioral;

---Full Adder procedure  is declared in package  to design 4 bit RCA

library IEEE;
use IEEE.STD_LOGIC_1164.all;
--------Package Declaration--------
package fa_proc is
procedure fa (a,b,c:in std_logic; signal sum,cout:out std_logic);
end fa_proc;
------Package Body ------
package body fa_proc is
procedure fa (a,b,c: in std_logic;signal sum,cout:out std_logic) is
 begin
 sum<= a xor b xor c;
 cout<=(a and b) or (b and c) or (c and a);
 end fa;
end fa_proc;

-------Using Package, design 4 bit RCA----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.fa_proc.all;

entity rca is
    Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
           sum : out  STD_LOGIC_VECTOR (3 downto 0);
           cin : in  STD_LOGIC;
           carry : out  STD_LOGIC);
end rca;

architecture Behavioral of rca is
signal c1,c2,c3:std_logic;
begin
fa(a(0),b(0),cin,sum(0),c1);
fa(a(1),b(1),c1,sum(1),c2);
fa(a(2),b(2),c2,sum(2),c3);
fa(a(3),b(3),c3,sum(3),carry);

end Behavioral;

Configuration Statement and Configuration Declaration in VHDL with example

Configuration statement
Objective: To design a full adder using two half adders which are written in different styles of modeling. For example one half adder using structural modeling and another using behavioral modeling.Half adders are given same architecture name.

--Half Adder behavioral 

entity ha is
    Port ( a,b : in  STD_LOGIC;
           s,c : out  STD_LOGIC);
end ha;

architecture Behavioral of ha is

begin
process(a,b) is
begin
if(a='0' and b='0') then s<='0'; c<='0';
elsif(a='0' and b='1') then s<='1'; c<='0';
elsif(a='1' and b='0') then s<='1'; c<='0';
else s<='0'; c<='1';
end if; end process;

end Behavioral;

---Half Adder using structural modelling
--note or gate declared but never used still binding is possible from the main program
entity xor_2 is
port (x,y:in std_logic;
z: out std_logic);
end xor_2;
architecture dataflow of xor_2 is
begin
z<= x xor y;
end dataflow;

-----or gate component----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_2 is
port (x,y:in std_logic;
z: out std_logic);
end or_2;
architecture dataflow of or_2 is
begin
z<= x or y;
end dataflow;

-----and gate component----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_2 is
port (x,y:in std_logic;
z: out std_logic);
end and_2;
architecture dataflow of and_2 is
begin
z<= x and y;
end dataflow;
--------main program-----------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ha is
    Port ( a,b : in  STD_LOGIC;
           s,c : out  STD_LOGIC);
end ha;

architecture structural of ha is

component xor_2 is
port (x,y:in std_logic;
z: out std_logic);
end component;
component and_2 is
port (x,y:in std_logic;
z: out std_logic);
end component;
begin
xor1: xor_2 port map (a,b,s);
and1: and_2 port map (a,b,c);

end structural;

---Full Adder structural program
entity fa is
    Port ( a,b,c : in  STD_LOGIC;
           sum,carry : out  STD_LOGIC);
end fa;

architecture fastructural of fa is
component ha is
port(a,b: in std_logic;
s,c:out std_logic);
end component;

component or_2 is
port(x,y:in std_logic;
z:out std_logic);
end component;
for ha1:ha use entity work.ha(Behavioral);--configuration statement binds instance ha1 with ha(behavioral)
for ha2:ha use entity work.ha(structural);--configuration statement binds instance ha2 with ha(structural)
signal s1,c1,c2: std_logic;
begin

ha1: ha port map(a,b,s1,c1);
ha2: ha port map(s1,c,sum,c2);
or1: or_2 port map(c1,c2,carry);


end fastructural;
  

VHDL code for Sequence Detector

Sequence -1011 
--Behavioral code of Mealy FSM for 1011 sequence detector

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity sd1011 is
    Port ( x,clk : in  std_logic;
           z : out  std_logic);
end sd1011;

architecture Behavioral of sd1011 is
signal state,nextstate:integer range 0 to 3;

begin
process(state,x)
begin
case state is
when 0 => if x='0' then nextstate<=0;z<='0';
 else nextstate<=1;z<='0'; end if;

when 1 => if x='0' then nextstate<=2;z<='0';
else nextstate<=1;z<='0';end if;

when 2 => if x='0' then nextstate<=0;z<='0';
else nextstate<=3;z<='0';end if;

when 3 => if x='0' then nextstate<=2;z<='0';
else nextstate<=1;z<='1';end if;

when others=> null;
end case; end process;

process(clk)
begin
if (rising_edge(clk)) then
state<=nextstate;
end if;
end process;

end Behavioral;

---- Second way to write same Mealy FSM behavioral model
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity sdz1011 is
    Port ( x,clk : in  std_logic;
           z : out  std_logic);
end sdz1011;

architecture Behavioral of sdz1011 is
signal state:integer range 0 to 3;

begin
process(clk)
begin

if (rising_edge(clk)) then

case state is
when 0 => if x='0' then state<=0;else state<=1; end if;

when 1 => if x='0' then state<=2;else state<=1; end if;

when 2 => if x='0' then state<=0;else state<=3; end if;

when 3 => if x='0' then state<=2;else state<=1; end if;
when others=> null;
end case;
if (state=3 and x='1') then z<='1'; else z<='0'; end if;
end if;
end process;

end Behavioral;

VHDL code for Sequence/Pattern Detector (0110)
---Dataflow model for the sequence 0110
---equations are from Mealy FSM + guidelines to reduce amount of logic(refer roth book)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sdd0110 is
Port ( x,clk : in  std_logic;
           z : out  std_logic);
end sdd0110;

architecture Behavioral of sdd0110 is
signal a,b:std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
a<= x and not b;
b<= x and ( a or b);
end if;
end process;
z<= not x and a and b;
end Behavioral;

Assignment 3

1. What is clock skew? Explain with neat diagram types of clock skew OR With suitable sketches and circuit diagrams briefly explain the concept of clock skew and clock jitter

2. Design a Mealy FSM to detect an overlapping sequence (i) “1011” (ii) 1101 and describe using VHDL.

3. Explain with neat diagram how asynchronous inputs are interfaced with synchronous digital circuits. (Hint: Synchronizer)

4. Write a VHDL code for up counter with synchronous and with asynchronous reset.

5. What is gating of clock? What are disadvantages of gating clock?

6.  Write a VHDL code  to  describe a 4 bit counter which  counts  only even numbers .0,2, 4,...,14,  0,2, ...

7. Implement using ‘generate’ statement a 4 bit shift register use D F-F as a component OR  Write a VHDL code using generate statement for 4-bit serial in serial out shift register using single D flip flop as a component.

8. Design a Moore FSM to design an overlapping sequence “1001” and describe using VHDL

9. Write a VHDL code for (i) Synchronous reset D flip flop (ii) JK flip-flop (iii) D flip-flop with asynchronous set and reset inputs. Draw entity diagram also.

10. Write a short note on Meta-stability. OR Explain the concept of meta-stability with suitable example. OR Explain the concept of meta-stability with suitable example. Which are the reasons because of which circuit enters into meta-stable state?  

11. Write a VHDL code for up down counter with control input up/down.

12. Describe the functioning of 'Process' statement with proper syntax. Write a VHDL code for positive edge triggered 'D' flip-flop with synchronous ‘Clear’ input.               

13. Convert following state table into its equivalent Moore model state diagram, and write a VHDL model for the same state diagram.

14. a) Write a VHDL model for single port RAM

       b) List and describe the i/o signals for dual port RAM and write a VHDL

15. Write VHDL code for 4 bit ripple counter using JK flip flop. Use structural modeling for writing the same.

16. Draw a state diagram for a sequence detector’1011’ which is realized as a Mealy machine.  Write a VHDL code for the above said Mealy machine.

17. Design and describe using VHDL a Data path to implement operations A=A+B, A=A-B, where A and B are 8 bit registers.

18. Explain the  working  of 4 input  bus  arbiter  having  fix  priority  with  the  help of state  diagram description  for  the  same.

19. Design  a two  input  'N  bit'  serial  adder  and  write  a VHDL  description  for  the same.(hint:  if  A and B are the  inputs  then  Sum=A+ B at every  clock  and cout  is  a carry  bit  which  is  stored for  further  additions  at  reset  the  stored  carry bit  is  cleared).